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DNR-CT-602-804
DNR-CT-602-804
High Speed Differential Counter/Timer Board
 
The DNA-CT-602-804 and DNR-CT-602-804 are high performance multipurpose interfaces for “Cube” and RACKtangle® I/O chassis respectively. The DNA/DNR versions are electrically identical and provide four independent channels, each having over voltage protection and opto-isolation. The 602-804 differs from the standard DNx-CT-602 in that it also implements a synchronous serial interface. Any of the 4 channels can be configured as a communications port or standard counter/timer.

Software included with the DNx-CT-602-804 provides a comprehensive yet easy to use API supporting all popular Windows programming lan- guages as well as programmers using Linux and most real-time operat- ing systems including QNX, RTX, VXworks and more. Finally, the UEIDAQ Framework supplies complete support for those creating applications in data acquisition software packages such as LabVIEW, MATLAB/Simulink, DASYLab or any application which supports ActiveX or OPC servers.
 
Characteristics:
  • For use in RACKtangle® I/O chassis
  • 4 independent channels, each can be configured as:
    • 32-bit counter timer
    • General purpose synchronous serial port (Tx, Rx, Clk, Trig, Ack)
  • Fully differential inputs/outputs at RS-422/485 logic levels
  • 10 Counting modes with 32-bit prescaler in counter mode
  • Supports SSI communications protocol in serial mode
  • Programmable data word and frame synch length in serial mode
 
Technical Specifications
COUNTER/TIMER Functions
Number of counter/timer units 4
Resolution 32 bits
Prescaler (per channel) 1 (32 bits)
Maximum frequency 16.5 MHz for external input clock; 
66 MHz for internal input clock; 
33 MHz for outputs
Minimum frequency no low limits
On-board FIFOs, per counter Input: 1024 x 32; Output: 1024 x 32
Minimum pulse width 15.15 nS
Minimum period 30.30 nS
Measurement resolution 15.15 nS (standard mode)
7.5 nS (2X mode)
Debouncer circuit size 16 bits (on GATE and CLKIN)
Compare registers per counter 2
External gates per counter 1, programmable polarity
External triggers per counter 1 (shared with Gate), edge sensitive, programmable polarity
SYNCHRONOUS SERIAL Ports
Baud Rate 300 to 16 Megabaud (2 Mb sustained, 4 Mb max per DNA/DNR chassis
Baud Rates available User selectable 0.1% accuracy or better
Data Word Length 3 - 32 bits
FIFO (on each channel) Input: 1024 word, Output: 1024 word
FrameSync phase control Programmable in 15.15 nS increments
General
Protection 7 kV ESD, 350V isolation
Input High / Low voltage RS-422/485 compatible
Electrical Isolation 350 Vrms, chan-chan and chan-chassis
Output High / Low voltage RS-422/485 compatible
Input/output buffer chip LTC1686 or equivalent
Power consumption 2W
Operating Temp. (tested) -40°C to +85°C
Operating Humidity 0 - 95%, non-condensing
Vibration IEC 60068-2-6 5 g, 10-500 Hz, sinusoida
IEC 60068-2-64 5 g (rms), 10-500 Hz, broad-band random
Shock IEC 60068-2-27 50 g, 3 ms half sine, 18 shocks @ 6 orientations
30 g, 11 ms half sine, 18 shocks @ 6 orientations