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PDL-DIO-64ST

PDL-DIO-64ST
64-channel, 16-bit PCI digital I/O lab board w/pattern generation
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64 digital I/O channels, high-speed pattern generation and digital streaming PCI digital I/O lab board.
 
Characteristics:
  • For PCI bus
  • 64 lines (5 V/TTL) of I/O in 16-bit ports
  • Generate interrupts on any line
  • Four separate high-speed IRQ lines (100 ns)
  • User-defined power-up state in 16-bit groups (High, Low, Tri-stated)
  • Two Enhanced Synchronous Serial Interfaces (ESSIs) for high-speed devices such as codecs
  • Three clock/interrupt lines, three 24-bit counters/timers
  • Onboard 16-bit FIFO: 2k samples
  • High-speed pattern generation and digital streaming (2 MS/s to and from disk)
  • PowerDAQ Software for Windows NT/2000/XP and Linux/RTLinux
 
Technical Specifications
DC Electrical Characteristics Over Operating Range
Input High Level Guaranteed logic High level 2.0V min
Input Low Level Guaranteed logic Low level 0.8V max
Input High Current VI = 5V ±1 μA max
Input Low Current VI = Gnd ±1 μA max
3-State Output Current t VO = 2.7V ±1 μA max
3-State Output Current t VO = 0.5V ±1 μA max
Short-Circuit Current VO = Gnd
(momentary)
-80 mA min 
-140 mA typ
-250 mA max
Input Hysteresis   100 mV typ
Output Drive Characteristics
Output Drive Current t VO = 2.5 V -32 mA per pin
-180 mA per port
Output High Voltage IOH = -3 mA 3.5V typ, 4.8V max
Output High Voltage OH = -15 mA 3.5V typ, 4.7V max
Output High Voltage OH = -32 mA 2.4V min, 3.0V typ
Output High Voltage OL = 64 mA 0.2V typ, 0.55V max
I/O Power Off Leakage VI/O ≤ 4.5V ±1 μA max
Counter /Timer
Prescaler 1 (21-bit)
Number of Channels 3
Resolution 24 bits
Maximum Frequency 16.5M S/s for external clock and
33M S/s for internal DSP clock
Minimum Frequency 0.0000002 S/s for internal clock, no low limit for external clock
Minimum Pulse Width 20 ns
Output High Level 2.0V min @ -4 mA
Output Low Level 0.5V max @ 4 mA
Protection 7 kV ESD,
±30V overshoot/undershoot
Input Low Voltage 0.0-0.8V
Input High Voltage 2.0-5.0V