| Technical Specifications |
| Analog Inputs |
| Resolution |
16 bit |
| Number of channels: |
Single-Ended |
16 |
| Pseudo-Differential |
16 |
| Differential |
8 |
| Max. sampling rate |
333 kS/s |
| Onboard FIFO |
1k samples |
| Channel gain list |
64 entries |
| Input ranges |
0-10V, ±5V, ±10V (softw. selectable) |
| Max working voltage for AIn |
single-ended |
±10V |
| differential |
±13V (signal + common mode) |
| pseudo-differential |
±13V (signal + EXT_GND) |
| Programmable gains |
1, 2, 5, 10 |
| Drift |
Zero |
±30 µV/°C |
| Gain |
±30 ppm/°C |
| Input impedance |
10MΩ |
| Input bias current |
±20 nA |
| Input Overvoltage |
±35V cont., 10mA max |
| A/D conversion time |
1.8 µs |
| A/D settling time |
3.0 µs (@ g=1) |
| DC Accuracy |
| Nonlinearity |
±1 LSB |
| System noise |
1.2 LSB |
| AC Accuracy |
| Effective number of bits |
14.8 |
| Channel crosstalk |
-80 dB @ 1kS/s |
| Clocking and Trigger Input |
| Max. A/D pacer clock aggregate throughput @ 0.01% accuracy |
333kS/s |
| External A/D sample clock maximum frequency |
333kS/s |
| Minimum pulse width |
20 ns |
| External digital (TTL) trigger: |
High-level input voltage |
2.0V min |
| Low-level input voltage |
0.8V min |
| Minimum pulse width |
20 ns |
| Digital trigger |
start/stop |
| Analog Outputs |
| Number of channels |
2 |
| Resolution |
12 bits |
| Update rate |
100 kS/s each |
| Onboard FIFO |
2k samples; 64k samples with
PD-64KMEM upgrade option |
| Analog output range |
±10V |
| Current output |
±20 mA max |
| Output impedance |
0.3Ω typ |
| Capacitive drive capability |
1000 pF |
| Nonlinearity |
±1 LSB |
| Protection |
short circuit to analog ground |
| Power-on voltage |
0V ±10 mV |
| Settling time to 0.01% of FSR |
10µs, 20V step; 1µs, 100mV step |
| Slew rate |
30 V/µs |
| Digital I/O |
| Input channels |
24 |
| Output channels |
24 |
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current |
2.0V min
0.8V max
20 µA
-20 µA |
Output driver high voltage
Output driver low voltage |
2.5V min, 3.0V typ (IOH = -32mA)
0.55V max (IOL = 64mA) |
| Current sink |
-32/64 mA max, lines 8-16
-24/24 mA max, lines 0-7
250mA per port |
| Counter /Timer |
| Number of channels |
3 |
| Resolution |
24 bits |
| Max frequency |
16.5 MS/s for external clock,
33 MS/s for internal DSP clock |
| Min frequency |
0.00002 Hz for internal clock,
no low limit for external clock |
| Min pulse width |
20 ns |
| Output high level |
2.0V min @ -4 mA |
| Output low level |
0.5V min @ 4 mA |
| Protection |
7 kV ESD, ±30V over/undershoot |
| Input low voltage |
0.0 - 0.8V |
| Input high voltage |
2.0 - 5.0V |
